[PCB design] Layout for SPI bus due to ringing

Michele Bertoni asked Jan 27,2022
0

Hi to all!
I always used SPI devices in low speed mode, now I need to push SPI clock at maximum device speed.
I'm using ADXL355 on evaluation board, directly connected to PIC microcontroller through 0.1" pitch connector.
On my first board I was using 0.3mm track width, 0.3mm track spacing and 0.3mm separation from ground plane.
Bus length was 18mm and I can see ringing but I can read at 6MHz clock speed.

On second design I decreased track width and separation to 0.18mm, increasing bus length to 35mm.
Due to misunderstanding there are no series resistor on SPI lines and rinnging encreased a lot, so I need to work at lower speed.
Core_3_2a.png


Can someone suggest me layout/solutions to avoid ringing on 0.18mm track width using 1.6mm PCB thickness?
Thanks.

Current layout:
Layout_5_3b_GP.png

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    I would place your pin out connections closer to the IC pads. You can also have the ground fill in between the SPI traces. You can also add optional locations for decoupling Caps on those lines <10nF.

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